In recent years, along with lower power dissipation in portable devices, as an operational requirement in lowering of voltage, there is a need to ensure a dynamic range of an output voltage on Vcc-side and to maintain a slew rate when there is a load variation. Power supply voltage Vcc is reduced from 5V to 4V or 3.3V, and ensuring a Vcc side maximum output is important. This becomes larger as a power supply voltage become lower.
FIG. 5 is a diagram showing a configuration of a signal output circuit disclosed in Patent Document 1. The signal output circuit is provided with a first and a second emitter follower circuit and a comparator 20.
The first emitter follower circuit has an NPN bipolar transistor T1 and a constant current source 12. A base of the transistor T1 is connected to an input signal terminal 52, and a collector is connected to a power supply terminal (Vcc) 56. The constant current source 12 includes an NPN bipolar transistor T2 and a resistor element R1. A collector of the transistor T2 is connected to an emitter of the transistor T1, a base is connected to a bias signal terminal (bias1) 54, and an emitter is connected to a ground terminal 58 via the resistor element R1.
The second emitter follower circuit has an NPN bipolar transistor T3 and a constant current source 14. A base of the transistor T3 is connected to the input signal terminal 52, and a collector is connected to the power supply terminal 56.
The comparator 20 receives output signals from the first and second emitter follower circuits, makes a comparison as to magnitude relationship between the received signals, and outputs a result. The comparator 20 includes transistors T5 and T6 forming a differential pair, a resistor element R3, and a current mirror circuit 30 including transistors T7 and T8. The resistor element R3 is connected between emitters of the transistors T5 and T6. The current mirror circuit 30 is connected to collectors of the transistors T5 and T6. The comparator 20 further includes PNP bipolar transistors T9 and T10, and constant current sources 42, 44, 46, and 48. The transistor T9 has an emitter connected to a base of the transistor T5, has a base connected to an output of the first emitter follower circuit (the emitter of the transistor Ti), and has a collector connected to the ground terminal 58. The transistor T10 has an emitter connected to a base of the transistor T6, has a base connected to an output of the second emitter follower circuit (the emitter of the transistor T3), and has a collector connected to the ground terminal 58.
The constant current source 42 is connected between an emitter of the transistor T9 and the power supply terminal 56. The constant current source 44 is connected between an emitter of the transistor T5 and the power supply terminal 56. The constant current source 46 is connected between an emitter of the transistor T6 and the power supply terminal 56. The constant current source 48 is connected between an emitter of the transistor T10 and the power supply terminal 56.
An output of the second emitter follower circuit (the emitter of the transistor T3) is connected to an external load 90. The comparator 20 performs voltage comparison between an output voltage Vo of the second emitter follower circuit and an output (the emitter of the transistor T1) voltage V2 of the first emitter follower circuit. When a voltage shift between Vo and V2 due to the external load occurs, the comparator 20 controls so that a current is supplied to the second emitter follower circuit (T3) connected to the load 90, by a bias supply circuit 60, and the voltage shift is remedied.
FIG. 6 is a diagram showing a configuration of a voltage generator disclosed in Patent Document 2. The voltage generator includes: an NPN bipolar transistor 8 having a base supplied with a voltage VOP output by an error detector (OP amplifier) 5 that receives a reference voltage VREF from a reference voltage generator 4 and a feedback voltage VFBK, to detect an error; a current mirror circuit including PNP bipolar transistors 10 and 11, which outputs a current obtained by multiplying a current flowing in the NPN bipolar transistor 8; and resistors 6 and 7 which cause generation of the feedback voltage VFBK to the error detector 5 from an output voltage VREG generated by current flowing in the current mirror circuit. A circuit of FIG. 6 is adapted to set an output voltage up to a power supply voltage Vcc-Vsat (saturation voltage between collector and emitter). An output voltage can be set by the feed back voltage VFBK which is an output of dividing resistors (R1 and R2) connected between an output 3 and GND and the reference voltage VREF from a reference voltage generator 4. At this time, the output voltage is constant. When an output current has become large, in order to be supply a PNP bipolar transistor 11, an output voltage VOP of the error detector (OP amplifier) 5 increases in order that a current flows to a PNP bipolar transistor 10, a collector current of the PNP bipolar transistor 10 increases, and a collector current of the PNP bipolar transistor 11 forming a current mirror with the PNP bipolar transistor 10, increases. By this configuration, stable voltage is obtained even when an output current fluctuates.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2006-311419A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2001-325034A
The entire disclosure of Patent Documents 1 and 2 is incorporated herein by reference thereto.
The following analyses are given by the present invention.
In the configuration shown in FIG. 5, an emitter follower is used by an NPN transistor as signal output, and maximum output voltage on the power supply voltage Vcc side is less than or equal to Vcc-Vbe (Vbe is emitter-base voltage). As a result, due to lowering of the power supply voltage Vcc, an output amplitude becomes smaller.
In the configuration shown in FIG. 6, an output voltage (DC) can be set to Vcc-Vsat on the power supply voltage Vcc side. However with regard to an AC signal and a pulse signal, when output is falling, an output signal waveform becomes dull (that is, slew rate decreases). In addition, in order to set a voltage, resistors 6 and 7 (R1 and R2) for determining set voltage are necessary. The circuit shown in FIG. 6 can cope with the increasing fluctuations of a current flowing through a load. When the current flowing through the load decreases, since there are resistors (R1 and R2) for setting the output voltage, the output signal waveform becomes dull.